System for controlled charging of stand-by storage batteries that supply a load on failure of power supply to the load from power mains

ABSTRACT

A system for controlled charging of a stand-by storage battery that supplies a load in the event of failure of a.c. power supply mains including high and low rate charging means energized by power from the mains to supply charging current to the stand-by battery selectively at high or low rates. This system includes a memory storage cell or device of low capacity relative to the stand-by battery which is connected to be charged in response to flow of discharge current from the stand-by battery only during stand-by operation of said stand-by battery while power supply from the mains is interrupted. The extent of charge thus received by the memory storage cell is proportional to the current actually discharged by the stand-by battery only while and if it is operative and discharging into the load during mains power failure. Upon restoration of power in the mains, the proportionately charged memory storage cell is caused to discharge automatically at a constant rate until exhausted and the discharge current of the memory cell is used to control circuit means to effect automatically high-rate charging of the stand-by battery from the mains until substantial exhaustion of the proportionate charge of the memory storage cell occurs, whereupon low rate charging of the stand-by battery from the mains commences automatically.

waited States Patent Godard June 6, 1972 s7 ABSTRACT A system forcontrolled charging of a stand-by storage battery Invent: Pierre Godard'y- 'g France that supplies a load in the event of failure of ac. powersupply [73] Assignee: So iem d A u l g fi a de mains including high andlow rate charging means energized Traction (Societe Anonyme) Romainvilleby power from the mains to supply charging current to the Francestand-by battery selectively at high or low rates. This system includesa memory storage cell or device of low capacity rela- Filed! 1969 tiveto the stand-by battery which is connected to be charged in response toflow of discharge current from the stand-by bat- [21] Appl' 887198 teryonly during stand-by operation of said stand-by battery while powersupply from the mains is interrupted. The extent [30] ForeignApplication Priority Data of charge thus received by the memory storagecell is proportional to the current actually discharged by the stand-bybat- Oct. 1, 1969 France ..6933547 tery only while and int is operativeand discharging into the load during mains power failure. Uponrestoration of power in ($1 the mains the proportionately charged memoryStorage Ce" is 58 f i 66 5 caused to discharge automatically at aconstant rate until ex- 1 I at hausted and the discharge current of thememory cell is used to control circuit means to effect automaticallyhigh-rate [56] References Cited 7 charging of the stand-by battery fromthe mains until substan- UNITED STATES PATENTS tial exhaustion of theproportionate charge of the memory storage cell occurs, whereupon lowrate charging of the stand- 3,356,922 12/ 1 9g; iohgston 3228296); bybattery f the mains commences automatically 3,480,791 11/19 es er3,483,393 12/1969 Gutzmer et al. ....307/66 19 Claims, 5 Drawing Figures"BREE.

3 I 2 g Zen L I 0 i I CHARGER swan-n i i: l l--' i srn. I

VOL'TG. I N P l STAGE I COI- RELAY "m y 0 t \5 v r'ii A o 1 I I "I luruonv I q PATENTEDJUH 6|972 SHEET 10F 4 o s-a tum INVENTOR PIERREGODARD ATTORNEYS PATENTEUJUH 61972 3,668, 11 8 SHEET 3 OF 4 oz fozlFIG.3

IFF. AMP IFI R I 8 m Ib INVENTOR man: eoomo A ORNEYS PATENTEDJUH 61972SHEET 0F 4 I' LE in 51 INVENTOR PIERRE GODARD BY RELATED APPLICATIONS Arelated application Ser. No. 865,546 filed Oct. 13, 1969 is pending.

BRIEF SUMMARY OF INVENTION The invention relates to recharging devicesfor stand-by storage batteries serving to supply a load in the event ofbreakdown of the normal power supply circuit from power mains. Theaforesaid load (for instance, light-supplying lamps) may be a stand-bysubstituting for the normal load which latter is no longer supplied bythe power mains. As a variant, the aforesaid load may be the normal loadusually supplied by the power mains, to which load, in the event of afailure or an interruption of the supply from the mains, the storagebattery is connected.

In the second case under consideration, the power supply mains are analternating current network supplying the load with rectified currentrectified by use of a suitable rectifier.

, It is this rectifier that is used also for the recharging of thestand-by battery.

As a rule, devices are provided to maintain the stand-by storagebatteries fully charged as a result of a charging system which, ifpermanent, is of moderate intensity. At the moment of occurrence of apower breakdown, the stand-by storage battery will take over the supplyoperation for a certain period during which it is being discharged and,the moment the restoration of power mains current recurs, the battery isautomatically returned to charge, however, at a low rate, in order tobecome again fully charged. At this low rate, however, a very longcharging period would be necessary and if a second power failure shouldoccur shortly thereafter substantially full recharge of the battery hadbeen effected, this might prevent in such event another required properstand-by operation of the battery in view of the fact that the latterwould not have become fully recharged when such need arose.

Systems have been provided to modify the rate of charge of the batteryby increasing the intensity of the charging current during a certaintime for the purpose of giving the battery as complete a charge aspossible within a very short time.

Through French patent l,2l 1,651 (U.S. Pat. No. 3,040,182) there isknown a direct voltage generator comprising an alternating current mainssupplying a rectifier at the terminals of which there has been connecteda battery of storage cells making possible the continuity of provisionof direct current in the event of breakdown or failure of the normal ACsupply. Such system comprises in addition a memory storage cell ordevice of a capacity that is low with respect to that of the stand-bystorage battery and capable of charging itself with a constant intensitycurrent In (as shown by curve (a) of FIG. 1 described below in which theabscissae represents the intensity current lb supplied by the stand-bybattery), from the stand-by storage battery during the shut-down time ofthe alternating current power Supply mains; thus, the charge received bythe memory storage cell is proportional to the shut-down time of thealternating current supply; this charge being used, the moment thealternating current supply is restored to permit recharging of thestand-by storage battery at a fast rate, by means of the charger;recharging of the standby battery of accumulators or storage cell beingperformed during the discharge time of the memory storage cell. Thus,the duration of the charge of the stand-by storage battery at a fastrate is equal to the duration of the discharge of the memory storagecell which is itself proportional to the duration of its charge which isin turn equal to the duration time of the breakdown of alternatingsupply current.

This system, even though it is an interesting one, is neverthelessattended by a certain lack of precision inasmuch as there does notalways exist a proportionality between the ampere-hours charged duringthe rapid charge of the stand-by storage battery and the ampere-hourscharged into the memory storage cell during the mains shut-down time: infact, even if the charging current of the memory storage cell during thecut-out of the mains can be well defined, the discharge current of thestand-by battery is not always well defined, and the same holds true forthat of its rapid charge in view of the fact that this chargerestitution may occur during the terminal period of charge of thestand-by battery when the efficiency of this operation is at itspoorest. It thus follows that, granted that there is a proportionalityof time in the memory system defined above, there is, however, neitheran identity nor even a proportionality of ampere-hours.

To improve this situation, another French patent 1,473,210 of Jan. 26,1966 provides for a memory in the form of a memory storage cell which isbeing charged, on the one hand, proportionally to the time of thedischarge of the main standby battery, hence the mains shut-down time,and on the other, proportionally to the current it discharges.

Nevertheless, in the system described in the latter patent, as shown bycurve (b)'ofFlG. l, with discharge currents of the stand-by storagebattery that are below a limit of la, The charging current of the memorystorage cell stays constant and it is only with discharge currents ofthe standby storage battery that are inexcess of lo that the chargingcurrent of the memory storage cell'is proportional to the dischargecurrent of the stand-by storage battery.

Moreover, in view of the fact that the charging of the memory storagecell takes places, in the case of substantial recharge currents of thestand-by storage battery, via a transistor, the proportionality factorbetween the current discharged by the stand-by battery and the chargingcurrent of the memory storage cell is modified under the effect oftemperature variations of said transistor, as well as the current limitlo forv putting the said transistor into operation. Of course, given avalue l of the discharge current of the standby battery, the aforesaidtransistor is saturated and its resistance is minimal. In that case, thecharging current In of the memory storage cell reaches its maximum valueand becomes constant.

Moreover, in both of the two systems just described each is. attended bya drawback inasmuch as the charging of the memory storage cell iscontrolled by the absence of the mains line current. If it should happenthat the stand-by storage battery would not be caused to supply currentto a load during the period of absence of mains line current, it wouldnevertheless be subjected to the fast-charge rate during a periodcorresponding to said absence.

It is an object of the instant invention to provide a novel memorysystem that is free of the aforementioned drawbacks. To this end, it isan object of the instant invention to permit the creation of an imagesignal of the current discharged by the stand-by storage battery, andthe integrating of said signal during time periods that do notnecessarily coincide with the periods during which the main line currentis absent, but with the periods during which the stand-by storagebattery actually discharges. In the application contemplated hereinafterof the device according to the invention for supervising or monitoringthe charging of a stand-by storage battery, the latter must bedischarging, because the control signal is provided by this verydischarge current. The system in accordance with the invention thenreacts proportionally to said current discharged by said battery, nomatter how weak that current may be, as can be seen from curve (c) ofFIG. 1.

Another object of the instant invention is a device for the charging ofa storage battery acting as a stand-by emergency" supply for a load inthe event of breakdown of a normal a. c. mains supply circuit, withcurrent associated with a charger whose input terminals are connected tothe said alternating current mains and whose output terminals areconnected to the said stand-by battery, said charger having a fast and aslow charging rate, a memory storage cell having a low capacity bycomparison with that of the stand-by storage battery which breakdown orinterruption of the alternating current supply from the mains and thatcontrols during its discharge period, in a discharge circuit, thefast-charging rate of the stand-by battery of accumulators,characterized by the fact that it comprises means for establishing avoltage proportional to the current discharged by the stand-by batteryinto the load, and a DC electronic amplifier for the amplifying of saidvoltage and itsconversion into a direct current the intensity of whichis proportional to said voltage, irrespective of the value of saidvoltage, said direct current passing through the said memory storagecell for the purpose of charging it proportionally to the currentdischarged by the stand-by storage battery and only if the latterdischarges into the load.

The invention will be readily understood by the description given belowof two modes of realization of the invention with reference to theannexed drawing in which: 7

FIG. 1 depicts graphs of operational characteristics of the invention incomparison with known systems;

FIG. 2 represents a block diagram of a system embodying the invention; IY FIG. 3 represents a detailed wiring diagram corresponding to the blockdiagram of FIG. 2;

FIG. 4 represents a diagram of a variant of the system in accordancewith the invention, and 7 FIG. represents a wiring diagram of the blockdiagram of FIG. 4.

DETAILED DESCRIPTION rent discharged by thebattery l during'stand-byoperation.

Said circuit comprises, in addition to the shunt 8, a differentialvoltage amplifier 10, connected to a voltage-current converter llsupplying a current toa memory storage cell or device. 12 during thetime of stand-by discharging operation of theb at'tery l. j i

The differential amplifier 10 and the voltage-current converter l1 arepolarized by means of a stabilized voltage supply source 7; saidstabilized voltage can be tapped from the battery 1 when the latterdischarging.

To this end, a relay 5, for the'detecting of absence of current from themains 2 controls the operation of the stabilized voltage supply source7.

The memory storage cell or device 12 which is discharging battery 1 andpermits the supply of the load 9 from the battery in the event of powersupply breakdown from mains 2.

'The terminal M of the shunt 8 is connected to a divider bridgecomprising the resistors-R, and R, and the variable potentiometer P,',the voltage at any selected point of the potentiometer being applied bya sliding contact 14 to the input of a voltage amplifier circuit 10provided with temperature-compensated transistors T, and T,.

The amplifier circuit 10 is of known design; it comprises twotransistors T, and T, advantageously enclosed in the same housing so asto standardize or equalize their temperature. The base of the transistorT, is connected to the sliding contact l4 of the low-resistancepotentiometer P,. Onthe other hand, the base of the transistor T, isconnected to the center point of a voltage divider composed of theresistors R, and R, respectively equal to. resistors R, and R iStabilized voltagesare tapped from the terminals of two Zener diodes DZ,and D2,, respectively, supplied with current by the battery 1 viaresistors R,, and 11,5, respectively when bridging contacts 19 and 20(normally open) are moved to closed condition. These'stabilizedvoltagesprovide forthe polarization of the'transistors T, and Tthe'moment the battery 1 is discharging, i.e., upon an interruption ofthe power supply at mains 2. To this end, the two normally open bridgingcontacts 19 and 20 of the line-monitoring relay 5 are respectivelyconnected in series with the resistors R,, andR said contacts beingclosed only in the event of the interruption of the alternating currentsupply in mains 2 which event de-energizes relay coil RL, of said relay5.

The resistor R, is 'connected to the terminal N of the shunt 8, also isconnected to the diodes D2,, DZ, and the resistors R, and Rareconnect'ed to the common connecting point of the diode DZ, and theresistor R,, whenever bridging contact 19 is in closed condition. v v tThe emitters of the transistors T, and T, are connected to the terminalN which is linked to the diodes D2,, D2,, and to the battery 1 via theresistors R,, R, and R,,. By means of the resistors'R, and R, ofidenticalvalue as resistors'R, and R,,

the collectors of the transistors T, andT, are connected to the commonconnecting point of diodeDZ, and resistor R,, wheneverbridging contact20 is in closing position.

. The output of the amplifier l0.is connected to the input of an outputamplifier which is a'voltage-current converter, comprising twotransistors T and T, respectively of thePNP and the NPN type andlikewise housed in a common housing,

' which provide for the equalization of their temperatures. To

during the operating periods of the stand-by storage battery 1 mally andpermanently via a charge-maintenance device 3 or,

after a breakdown or another interruption of supply from mains 2, duringwhich the battery discharged into a load 9, by

means of a supplementary fast-charging device 4.-

. In addition, the rectangle A shows in dot-dash lines the circuit forthe creation and integration of a current the intensity reduce to aminimum the temperature drift of the amplifier 11, the 'PNP transistorT5 controls the NPN transistor T, in such a way as tocancel theemitter-base threshold voltage variation of the transistor T, by anidentical variation of the transistor T The polarization voltages of thetransistors T and T, are likewise tapped off from the respectiveterminals of diodes DZ, and D2,. The circuit of output amplifier 11 isarranged as follows: the base of its transistor T, is connected to theoutput of the amplifier 10, i. e. to the collector of transistor T andof which is proportional to that of the current .discharged by thestand-by battery 1 into the load 9.

To this end there is shown, series-connected between the battery 1 andthe load 9, the shunt 8 providing between its terminals M (connected tothe positive pole of the battery 1) and N (connected to the load 9) avoltage proportional to the current discharged by the battery 1.

A monitored or controlled bridging contact 21 of a relay 5 is arrangedbetween the load 9 and the negative terminal of the the emitter of thetransistor T, is connected via the resistor R9 to the shunt terminal Nalready connected with diodes DZ, and D2 Its collector is connected tothe common connecting point of resistor R,, and diode D2,.

The base of the transistor T, is connected to the emitter of transistorT its collector is connected through a memorystorage cell or device 12via a diode D, and a resistor R to the terminal N of shunt 8 with thediode D, blocking the discharge of the storage cell 12 into the circuitof the amplifier l l, and the emitter of transistor T is connected, viaa resistor R to the common connecting point of resistor R,, and diodeD2,.

Under normal operation of the supply at mains 2, the coil RL, of therelay 5 is energized, bridging contacts 19, 20 and 21 then beingmaintained in open condition. The battery 1, therefore, does notdischarge; it is then being charged at slow charging rate by means ofthe trickle charge of slow rate maintenance charging device 3; since thecontacts 19 and 20 are then open, the amplifier circuits l and 11 arenot polarized and consequently the memory storage cell 12 does notreceive any charge.

The moment a failure occurs in supply of current from mains 2, the coilRL becomes de-energized and the bridging contacts 19, 20, and 21 thenmove to circuit closing condition. By means of the closed bridgingcontact 21, the battery 1 then supplies the load 9.

Simultaneously, the then closed bridging contacts 19 and 20 permit thepolarization of the amplifiers l0 and 11 via the stabilized voltagesource diode D2,, diode DA supplied by the battery 1 via shunt 8 as longas the coil RL, of line monitoring relay is de-energized resulting fromand detecting an interruption of the power su ply from mains 2, Le.during a time t that this interruption lasts, provided, of course, thatthis time t does not exceed time I, of a complete discharge of thebattery 1.

By way of example, the values of resistors R,, R R and R and thepotentiometer P can be adjusted in such a way that the bases of thetransistors T and T will be at an identical potential the moment theshunt 8 is being traversed by a current equal to, e. g. one-half therated discharge intensity of the battery 1. The current passing throughthe resistor R, is then divided equally between the resistors R and Rand the collector potentials of the two .transistors T and T, then areequal. The shunt 8 is designed to provide only a very slight voltagedrop in the order of 0. l volt, for rated current intensity.

lf, for example, a discharge current lb from the battery 1 into the load9 flows through the shunt 8, the voltage drop at the terminals M and Nof the shunt 8 is added to the stabilized voltage applied to the RrPyRadivider between the point M and the common connecting point of diode DZand resistor R The voltage, therefore, between base-emitter of thetransistor T falls if current lb is higher than half the rated dischargeintensity of the battery 1, and current flow diminishes in thetransistor T the voltage drop tends to become lower in the resistor Rand current flow increases in the transistor T and in the resistor R Thepotential applied to the base of the transistor T then becomes morepositive, i. e. its polarization diminishes. The transistor T thencontrols the transistor T,. which becomes more conductive as a resultand a current 1 passes through memory storage cell 12 and charges it.

The transistor T is polarized by the resistor R and the transistor Tshunts all or part of the polarization current, depending on the stateof the differential amplifier 10.

The resistor R limits the maximum charging current of the memory storagecell 12 (especially in the event of substantial intensity peaks in theload).

The diode D blocks the discharge of the memory storage 12 into theamplifier circuits l0 and 11 during the period when the voltagesstabilized at the terminals of diodes DZ, and DZ are inoperative duringtime supply from mains 2 is operative.

The memory storage cell 12 which is initially completely discharged isfirst charged with an amount of electricity lt which is chosen so as tobe of a capacity of the order of the double of It which is the maximumcharge corresponding to a complete discharge of the battery 1.

In brief, the shunt element 8 transforms the current lb (supplied by thebattery 1 to the load) passing through it into a signal of a voltage ustrictly proportional thereto and which is available at its terminals Mand N. The signal voltage u is then amplified in amplifier l0 andsubsequently reconvened and amplified into an intensity I in amplifierconverter 11. Said intensity l is then directed into the memory storagecell 12 that performs its integration in this time and becomes chargedby current I, proportional to the current lb discharged by the battery 1into the load 9 via the shunt 8.

The memory storage cell 12 is connected to a discharge circuitcomprising the resistors R and R, via a bridging contact 22 likewisecontrolled by the coil RL, of the relay 5. This contact 22 is closedwhen coil RL, is energized. This discharge circuit is also connected toa control circuit comprising two transistors T and T The base of thetransistor T, is connected to the common connecting point of resistors Rand R and its emitter is connected to the terminal N of shunt 8. Thecollector of the transistor T, is connected, on the one hand, jointly tothe maintenance charger 3 and to the fast charger 4 via a resistor R anda normally closed bridging contact 23 controlled by the relay 5, and onthe other hand, also directly to the base of the transistor T Theresistor R is likewise connected via a resistor R and a coil R1 of acontrol relay 6 to the collector of the transistor T the emitter oftransistor T being connected to the terminal N of shunt 8. v

The coil RL. controls a bridging contact 24 making possible the supplyof the fast charger 4 from the alternating current supply mains 2 whenpower is on.

The moment current re-appears or is restored in the supply mains 2, therelay coil RL, of the monitoring relay 5 is re-energized; the bridgingcontacts 19, 20, and 21 then open, thereby cutting off the currentsupply of the amplifiers l0 and 11 from the battery 1 and cutting theload 9 out of the circuit; simultaneously, the two other bridgingcontacts 22 and 23 of the relay 5 move to circuit closing condition.

Through the closed bridging contact 22, the memorystorage cell 12 thendischarges into the resistors R and R This results in the polarizationof the transistor T, which shortcircuits that of the transistor T thelatter which is thus blocked then controls putting into operation thefast charger 4 at a heavy rate (fast charge). This control is performedby the relay coil R1 which, the moment it is not traversed by anycurrent, will permit its bridging contact 24 to close, which permits thecurrent supply of the charger 4 from the power main 2. It is, of course,understood that any other fast-charge system could be used within theframework of the instant invention.

Toward the end of the discharge of the memory storage cell 12, thetransistor T becomes blocked and this unblocks the transistor T With thelatter becoming conductive, the relay coil RL of relay 6 becomesre-energized. This opens its bridging contact 24 and cuts off the rapidcharge of the battery 1. Charging of battery 1 then continues to beprovided at usual maintenance rate by the slow charger 3. The resistorsR and R serve to limit the intensity of the current in the transistors Tand T respectively.

FIG. 4 illustrates a block diagram of a variant of the invention. Insaid figure, the elements identical to those of FIG. 2 bear the samereference characters as those used in FIG. 2 except that these areprimed.

Thus, the alternating current supply mains 2 supplies via a charger 3connected to a voltage level charging device 4' a stand-by storagebattery 1'. The charger 3' provides for the maintaining of the battery 1at full charge when the line supply 2' operates normally, i. e. whilethe battery 1 does not discharge into the load 9', while it provides forfast recharging of the battery under the effect of the fast charger 4following a discharge of the battery into the load 9'. The battery 1'supplies the load 9' via the shunt 8' in the event of a breakdown orfailure of the alternating current supply mains 1; in this embodiment,the load 9' shown is the load that is normally being supplied by themains 2'.

A voltage 14 available at the terminals of the shunt 8' when the load 9is supplied by the battery 1' is amplified in an amplifier stage 10'connected to a current amplifier stage 11', said two amplifier stagesbeing supplied by a source of stabilized current 7' tapped from thebattery 1' when the latter discharges into the load 9'.

The amplifier stage 1 l is connected to the memory storage cell 12' viaa separator or blocker 13 that acts to render inoperative or cut offthis charging current path as long as the supply voltage is availablefrom mains 2'. Any other equivalent means to cut off its charge or makeit inoperative may be used.

In the event of failure of the line voltage at mains 2, the separator orblocker 13 re-establishes a connection so that the discharge of thebattery 1' can be recorded by the memory storage cell 12.

A stabilized voltage source 17 supplied upon the presence of the linevoltage in supply mains 2' by an auxiliary circuit, and which in turnsupplies the separator or blocker 13 with voltage, a discharge circuit14, a centralizing element 15, and a manually controlled delayingcircuit 16 makes possible the omission of a relay sensitive to thepresence of the line voltage similar to relay 5 of FIGS. 2 and 3.

If the supply at mains 2' is re-established following an interruption,said source 17, re-supplied, acts on the separator or blocker element 13to cut ofi the charge circuit of the memory storage cell 12', and on thedischarge circuit 14 and a centralizing element 15 in such a way thatthe discharge circuit 14 of the memory storage cell 12 transmits theinformation supplied by the memory storage cell 12 to the centralizingelement 15 which then permits the operation at fast charge from thecharging unit 3'-4'. This approv can be supplied also by the manuallycontrolled delay element 16 by means of the push-button key 8,, via theelement 15. g

This delaying element 16 makes it possible to charge the battery 1' whenthe memory device 12 has not been charged as a result of a discharge ofthe battery 1'. This may be the case if the installation has for sometime been disconnected from the mains 2' and the self-discharge of thebattery 1' has not been compensated for by a maintenance charge from 3'.

A device 18 (dotted line) which is not indispensable for the puttinginto practice of the invention, which is, however preferably combinedwith it, is connected between the centralizing element 15 and thecharger 3-4'. This may be the device disclosed by copending applicationSN 865,546 filed on Oct. 13, 1969 entitled Thermally responsivecontrolled charging arrangement for storage batteries". This said device18 is a controlled charging arrangement for a storage battery,comprising means which, depending on the difference between ambient andbattery temperatures, measured by means of probes, control the chargingof the battery 1 The advantage of use of such a device 18 resides in thefact that it makes it possible under certain circumstances upon thecharging of the battery at constant voltage, especially when thetemperature of the battery is rather high, to interrupt the fast-ratecharge the moment the battery has been charged, to

. avoid overcharging it.

Indeed, if the temperature is high, the charging current tends to bevery high and then the complete discharging of the memory storage cell.12 might, under extreme conditions, cause an overcharging of thebattery 1 The device 18 may likewise be used with the delaying element16 since the timing of the latter does not depend on the extent ofdischarge of the battery.

FIG. 5 shows the circuitry of the system of FIG. 4, wherein the ac powersupply mains 2' activates the charger 3'.

The battery 1' connected to the conduits L2 and L4, is connected to twooutput terminals of the charger 3' and it is likewise connected byconduits L1 and L4 to terminals 9a and 9b for connection to the load 9'.

In the load line L1 the shunt 8' is included a part of the voltage ofwhich is applied to the inputs a and b of 'the amplifier stage 10' viathe voltage divider formed by the resistors R R and the potentiometer Pand by the resistors R R and This amplifier stage 10 is, in thisinstance, a high-gain integrated circuit thus making it possible toachieve elimination of one transistor in the following amplifier stage11 (e.g. T of FIG. 3). In addition to the inputs a and b, this amplifierstage 10 comprises one output 3, two supply inputs c and d, and are-injection input r.

The stage 1 1' comprises mainly the transistor T the base of which isconnected to the output s of the amplifier 10' via the resistor R ltsemitter is connected to the Zener diodes DZ' DZ',, forming the source ofstabilized voltage 7', via resistors R and R Its collector is connectedto the low-capacity memory accumulator 12 (low capacity with respect tothe battery) via the resistor R and the diode D10, and to the otherterminal of the stabilized voltage source 7 (formed by the Zener diodesD2, and DZ,) via the resistor R and the collector-emitter junction ofthe transistor T, that forms the main part of the separator or blockerstage 13.

The source of stabilized voltage 7 formed by the Zener diodes D2, andDZ, is supplied by the battery 1 via lines L2 and L4 and the resistor Rand also supplies the integrated amplifier stage 10 via the inputs c andd.

The condenser C is intended to prevent the likelihood of the occurrenceof auto-oscillations of the amplifier stage 10'.

The resistor R makes possible a more reliable blocking of the transistorT in the event of the absence of a voltage signal at the terminals ofthe shunt 8.

The transistor T forming the main part of the separator or blocker stage13 is polarized by the resistors R and R at the terminals of a Zenerdiode D2, forming the source of stabilized voltage 17 supplied by theauxiliary output terminals of the charger 3, which are connected to theconduits L2 and L3. Stabilized voltage source 17 is completed by ashunting condenser C providing for the filtering of the voltage suppliedby said source 17. Y

The memory storage cell 12' receives its charging current from thebattery 1' as has been shown, via the stabilized voltage source 7 thevoltage of which is transmitted by the amplifier stage 11' (transistor Twith a diode D; which shunts a resistor R completing the chargingcircuit of said memory storage cell 12. It is discharged into thedischarge circuit 14 by a special discharge circuit composed of theresistor R and a transistor T the emitter voltage of which is fixed bysaid resistor R and whose base polarization is provided by the resistorsR R and a variable potentiometer P5. This special discharge circuitconstituted essentially of a transistor T the emitter of which ispolarized by a resistor R5,, traversed by the discharge current of saidmemory storage cell 12', has the effect of supplying a constant currentdischarge, which was not the case with the system shown in FIG. 3 (inwhich the memory-storage cell was discharged mainly into the resistorsmemory storage cell 12', acts as a temperature-compensating element forthe transistor T with their junction voltages obeying a law of identicalvariation the moment the temperature varies. A second discharge circuitof the memory storage cell 12 transmits a signal to the base of atransistor T and is formed by the collector-emitter circuit of atransistor T polarized by resistors R and R connected across the terminals of the stabilizing voltage source 17 and a resistor R Thetransistor T itself constitutes a part of the centralizing element 15that authorizes or controls the actuation of the fast-charging device 4'which raises the voltage of the charger 3'. In FIG. 5, there is shown,by way of example, a relay RL, connected to the collector of transistorT the bridging contact 25 of which controls the actuation of the chargevoltage raising device 4. It would be possible to substitute atransistor circuit for the relay RL. The circuit of the centralizingelement 15 is completed by a second bridging contact 26 or an equivalentelement controlled by the temperature differential response device 18referred to above which makes it possible to stop the fast-charge of thebattery 1', for example, as a function of the temperature of the saidbattery.

The centralizing element 15 also comprises another transistor T16 theemitter and collector of which are mounted in parallel with the emitterand the collector of transistor T Said transistor T just as transistor Tauthorizes the fastcharging of the battery, however, it is controlled bythe delaying circuit 16 of FIGS. 4 and 5. Said delaying circuit 16 iscomposed of an storage cell (of low capacity) which will be charged ifpower is present in mains 2' by the stabilized voltage source 17 via aresistor R Said storage cell 120 discharges into the resistors R R and Reither via the emitter-collector/circuit of a transistor T or via thecircuit of the pushbutton B, across the terminals of which there is acondenser C The resistor R polarizes the transistor T The transistor T,is polarized by a transistor T by means of a resistor R which isconnected to the collector of T, while the emitter of the latter isconnected to one of the temiinals of the accumulator 120. The resistor Ris connected to the base of T A resistor R shunts the emitter-basecircuit of the transistor T In the operation of the device shown in FIG.5, three cases can be differentiated:

l. ABSENCE OF POWER LINE VOLTAGE AT MAINS 2'.

If the battery 1' does not discharge into the load 9', the shunt 8' doesnot show any voltage drop, and the output voltage at s of the amplifierstage 10 is inadequate to polarize the transistor T so that the memorystorage cell 12' does not receive any charging current. I

The moment the battery 1' discharges into the load on occurrence of amain power line failure, the shunt 8' has a voltage appearing across itsterminals that is amplified by amplifier stage 10' and polarizes thetransistor T more or less as a function of the value of said voltageacross the terminals of the shunt 8 in such a way that the memorystorage cell 12' receives a charging current proportional to saidvoltage and defined by the resistor R and the amplifier stage outputvoltage. The resistor R limits the charging current to accumulator 12 toa specified maximum value, the moment high current peaks exceed therating of the shunt 8'.

The resistor R through which the charging current of thememory-accumulator 12' is passing defines a voltage drop that isreinjected at the input terminal a of the amplifier 10 thereby determingthe gain of said amplifier stage 10'. This counter-reaction eliminatesthe effects of the temperature variations to which the transistor T,,,,the Zener diodes DZ and DZ' and the amplifier stage 10' are likely to besubjected.

2. VOLTAGE RETURNS TO THE MAINS 2'.

At that moment, the stabilized voltage 17 (Zener diode D2 is suppliedand the transistor T is polarized by the resistors R and R and shuntsthe current supplied by the amplifier stage 10'. The diode D preventsthe discharging of the memory storage cell 12 through T The memorystorage cell 12 then discharges at a constant intensity by virtue of thefact that the emitter-collector junction of the transistor Tisseries-connected with the resistor R along the discharge path ofstorage cell 12' and that the polarization of the base of saidtransistor T has been suitably regulated by adjustment of potentiometerP The storage cell 12' at the same time polarizes the transistor T-, bymeans of the resistor R by passing current through the transistor Twhich is rendered conductive through the energization of the source 17.The transistor T that has been rendered conductive then energizes therelay RL (bridging contact 26 being closed) which thus closes thebridging contact 25 and the battery 1' is put under charge at the highvoltage level (high charging rate).

This charge lasts as long as the transistor T is conductive and thecontrol 26 remains closed.

The transistor T remains conductive as long as the voltage of the memorystorage cell 12" is adequate to provide its polarization and as long astransistor T remains conductive by virtue of the presence of the powersupply in mains 2'. The open or closed condition of bridging contact 26is controlled by the temperature compensating device 18 that is capableof cutting 0E the charge at high-voltage level as a function, forinstance, of the battery temperature level.

The moment the memory storage cell 12' is discharged, its voltagebecomes insufficient to maintain the polarization of transistor T-,, andthe contact 25 opens since at such time the relay RL is no longerenergized. Then, charge of battery l is only from maintenance charge 3.

3. MANUALLY CONTROLLED CHARGING OF THE BATTERY The battery can becharged under manual control without charging the memory storage cell 12and the period of the charge at high voltage will be determined by thestorage cell 120. To that effect, depression of the pushbutton B, iseffected and short circuits the emitter-collector junction of transistorT Since the accumulator discharges into the resistors R and R thetransistor T becomes conductive and the relay RL is energized. Thepolarization of the transistor T is maintained by the transistor T viathe resistor R the moment the push-button B, is released. Charging stopswhen the storage cell 120 no longer has a voltage adequate to polarizethe transistors T T and T Variations are, of course, possible in thesystems disclosed within the scope of the appended claims. No intentionof limitation to the exact abstract or specific embodiments describedexists.

What is claimed is:

1. That improvement in load supplying systems wherein a load isalternatively supplied either by power mains or by a stand-by storagebattery upon occurrence of power failure at the mains comprising astorage battery recharging system for charging the battery selectivelyat high and low charge rates, a memory storage cell of low capacityrelative to the stand-by storage battery, means for charging the memorystorage cell to an extent directly proportional to the total amount ofcurrent discharged by the stand-by storage battery while the latter issupplying current into the load during power failure at the mains, saidmeans comprising a shunt circuit including a shunt resistor throughwhich a portion of the total current discharged into the load by thestand-by battery at all times passes during discharge of the stand-bybattery to provide a potential across said resistor directlyproportional to the total current passing through said resistor, meansfor stabilizing and amplifying said potential and applying it to saidmemory cell to thereby charge said memory cell proportionately to thetotal current discharged by the stand-by storage battery, and meansresponsive to discharge of the proportionately charged memory cell onrestoration of power supply at the mains to institute and maintain highrate charging of the stand-by storage battery from said mains for aperiod of time that is a function of the total proportionate chargereceived by the memory cell from the total quantity of current actuallydischarged by the stand-by battery into the load and means forthereafter establishing low rate charging of said stand-by battery fromthe mains.

2. That improvement in load supplying systems according to claim 1including a stabilized voltage source energized by said storage batteryto supply a polarizing control current to said amplifying means thatprovides for charging of said memory storage cell when failure of powersupply at the mains occurs.

3. That improvement in load supplying systems according to claim 1including monitoring means controlled by discharge of said memorystorage cell and sensing means responsive to restoration of power supplyin the power mains after failure monitored by said monitoring means toeffect charging of the storage battery at high rate upon suchrestoration of power supply in the mains.

4. That improvement in load supplying systems according to claim 1wherein said stabilizing and amplifying means comprises a firstsymmetrical transistorized differential amplifier provided withautomatic compensation for temperature variations and transistorizedconversion means for the amplified voltage also provided withcompensation for temperature variations, and a stabilized voltage sourceenergized by said storage battery to supply a polarizing control currentfor said voltage amplifying means, said stabilized voltage sourcecomprising Zener diodes connected to terminals of said storage battery.

5. That improvement in load supplying systems according to claim 3wherein said sensing means comprises a relay responsive to presence ofpower supply in the power mains and said monitoring means comprises asecond relay responsive to presence of discharge from said memorystorage cell.

6. That improvement in load supplying systems according to claim 2including a circuit means supplied by a second stabilized voltage sourcesupplied by the power mains to prevent charging of said memory storagecell while power supply exists in the mains,- and also including acentralizing system authorizing fast rate charging of the storagebattery from the mains whenever discharge of the memorystorage cell iseffected. v

7. That improvement inload supplying systems according to claim 6including means to effect discharge of the memory storage cell at asubstantially constant value.

, 8. That improvement in load supplying systems according to claim 1wherein said stabilizing and amplifying means. comprises ahigh-gainintegratedamplifier circuit whose input terminals are connected toreceive a fraction of the voltage across the shunt, resistor means toreinject into said circuit a voltage drop proportional to said currentcharging the memory storage cell to fix the gain of said amplifiercircuit and to eliminate effect of temperature variations,transistorized conversion means forthe amplified voltage of said voltageamplifier means comprising two Zener diodes connected to the storagebattery and a transistor polarizable by said two Zener diodes, andcircuit means to prevent charging of the memory storage cell while poweris supplied by the mains, said last named circuit means comprising otherZener diodes connected to be supplied by the power mains and atransistor polarizable by said other Zener diodes. v

' 9. That improvement in load supplying systems according to claim 8including also a centralizing system comprising a relay controllingtransistor and a relay connected thereto, said last named transistorbeing rendered conductive by simultaneous presence of power in the mainsand of a'discharge current from the memory storage cell. 7

10. That improvement inload supplying systems according to claim 7wherein said means to effect discharge of the memory-storage cell atsubstantially constant value comprises a discharge circuit including atransistor and a resistor connected for passage through itof dischargecurrent from the memory storagecell, said last-named transistor havingan emitter which is polarizable by the discharge current passingthrough'the resistor.

11'. That improvement in load supplying systemsaccording to claim 1wherein said storage battery recharging system for charging selectivelyat high and low charge rates includes means for effecting charging atthe selected rates at respective different constant voltages, andtemperature sensitive means I includes transistors.

fecting such discharge of said additional low a a 12' a the high ratecharging means to activate the latter upon discharge of such lowcapacity storage cell and serve as an additional control forestablishing fast high rate charging of the storage battery, and manualcontrol means connected for efcapacity storage cell. v I

13. That improvement in load supplying system according to claim 1wherein said means for charging the memory storage cell comprisetransistors and wherein said means responsive to discharge of current ofthe charged memory storage cell on restoration of power supply at the,mains also 14. That improvement in load supplying systems according toclaim 13 include temperature compensation means for all saidtransistors'1 15. That improvement in load supplying systems wherein theloadalternatively is supplied by power from power mains, and by astand-by'storage battery upon failure of power supply from thecomprising a storage battery recharging system for charging the batteryfrom the mains selectively. at a high and low charge ratesandeomprisinga memorystorage cell of low capacity relative to that ofthe storage battery. circuit means including transistors connected foreffecting charg ing of the memory storage cell by discharge current fromthe storage battery and proportionately to the total amount of currentdischarged therefrom while the latter is supplying the load on failureof power from themains, circuit means including transistors connectedbetween the memory storage cell and said battery recharging system topennit discharge current flow from the proportionately charged memorystorage cell on restoration of powersupply in the mains to activate saidstorage battery charging system to high charge rate until dischargecurrent flow from said proportionately charged memory storage cellsubstantially ceases,'and means to thereafter reestablish low chargingrate of the storage battery from said recharging system.

16. That improvement in load supplying systemsaccording I to claimlsincluding relaymeans to cut off supply of the load by the storagebattery while power is being supplied by the 17. That improvement inload supplying systems according to claim 15 including also circuitmeanscomprising-transistors and a relay connected, to the battery rechargingsystem to discontinue automatically its charging at high rate and effectrestoration of charging" at low rate at substantial cessation ofdischarge current flow from said memory storage cell.

18. That improvement in load supplying systems according to claim 15including'meansresponsive to storage battery temperature and switchingmeans operated therebyto change said battery recharging system from highrate to low rate charging irrespective of the charge condition of saidmemory storage cell when the storage battery temperature exceeds adetermined value during high rate charging thereof.

for. controlling the time of high rate charging of the storage batteryas necessary.

12. That improvement in load supplying systems wherein the load isalternatively supplied by power mains and by a stand-by storage batteryupon occurrence of failure at the power mains comprising a storagebattery recharging system including means to charge the batteryselectively at fast high rate and means to charge the battery at slowlow rate from the power mains, means to control automatically the fasthigh rate charging time, said last-named means comprising a memorystorage cell connected to be charged bythe storage battery only whilethe latter is discharging into the load on occurrence of power failureand proportionately to the. total amount of electricityactuallydischarged by the storage battery into the load, and circuit means fordelivering discharge current from the proportionately charged memorystorage cell to activate the high rate charging means of the storagebattery upon restoration of power supply in the mains, an additional low19. That improvement in load supplying systems wherein a load isalternatively supplied either by power mains or a standby storagebattery upon occurrence of power failure at the mains, comprising astorage battery recharging system for charging the battery selectivelyat high and low charging rates, a memory storagedevice of low capacityrelative to the standby storage battery, means for charging said memorystorage device to an extent directly proportionate to the total amountof current discharged by the stand-by battery while the latter issupplying current into the load during power failure, and automauc meansresponsive to operation of the proportionately charged memory storagedevice effective on restoration of power supply at the mainsautomatically to' initiate and maintain high rate charging of thestand-by battery from said mains for a period of time that is a functionof the total charge received by the memory storage device during actualdischarge of the stand-by battery, and means for thereafter establishinglow rate charging of said stand-by battery from the mains.

a ha a It

1. That improvement in load supplying systems wherein a load isalternatively supplied either by power mains or by a stand-by storagebattery upon occurrence of power failure at the mains comprising astorage battery recharging system for charging the battery selectivelyat high and low charge rates, a memory storage cell of low capacityrelative to the stand-by storage battery, means for charging the memorystorage cell to an exTent directly proportional to the total amount ofcurrent discharged by the stand-by storage battery while the latter issupplying current into the load during power failure at the mains, saidmeans comprising a shunt circuit including a shunt resistor throughwhich a portion of the total current discharged into the load by thestand-by battery at all times passes during discharge of the stand-bybattery to provide a potential across said resistor directlyproportional to the total current passing through said resistor, meansfor stabilizing and amplifying said potential and applying it to saidmemory cell to thereby charge said memory cell proportionately to thetotal current discharged by the stand-by storage battery, and meansresponsive to discharge of the proportionately charged memory cell onrestoration of power supply at the mains to institute and maintain highrate charging of the stand-by storage battery from said mains for aperiod of time that is a function of the total proportionate chargereceived by the memory cell from the total quantity of current actuallydischarged by the stand-by battery into the load and means forthereafter establishing low rate charging of said stand-by battery fromthe mains.
 2. That improvement in load supplying systems according toclaim 1 including a stabilized voltage source energized by said storagebattery to supply a polarizing control current to said amplifying meansthat provides for charging of said memory storage cell when failure ofpower supply at the mains occurs.
 3. That improvement in load supplyingsystems according to claim 1 including monitoring means controlled bydischarge of said memory storage cell and sensing means responsive torestoration of power supply in the power mains after failure monitoredby said monitoring means to effect charging of the storage battery athigh rate upon such restoration of power supply in the mains.
 4. Thatimprovement in load supplying systems according to claim 1 wherein saidstabilizing and amplifying means comprises a first symmetricaltransistorized differential amplifier provided with automaticcompensation for temperature variations and transistorized conversionmeans for the amplified voltage also provided with compensation fortemperature variations, and a stabilized voltage source energized bysaid storage battery to supply a polarizing control current for saidvoltage amplifying means, said stabilized voltage source comprisingZener diodes connected to terminals of said storage battery.
 5. Thatimprovement in load supplying systems according to claim 3 wherein saidsensing means comprises a relay responsive to presence of power supplyin the power mains and said monitoring means comprises a second relayresponsive to presence of discharge from said memory storage cell. 6.That improvement in load supplying systems according to claim 2including a circuit means supplied by a second stabilized voltage sourcesupplied by the power mains to prevent charging of said memory storagecell while power supply exists in the mains, and also including acentralizing system authorizing fast rate charging of the storagebattery from the mains whenever discharge of the memory storage cell iseffected.
 7. That improvement in load supplying systems according toclaim 6 including means to effect discharge of the memory storage cellat a substantially constant value.
 8. That improvement in load supplyingsystems according to claim 1 wherein said stabilizing and amplifyingmeans comprises a high-gain integrated amplifier circuit whose inputterminals are connected to receive a fraction of the voltage across theshunt, resistor means to reinject into said circuit a voltage dropproportional to said current charging the memory storage cell to fix thegain of said amplifier circuit and to eliminate effect of temperaturevariations, transistorized conversion means for the amplified voltage ofsaid voltage amplifier means comprising two Zener diodes connected tothe storage battEry and a transistor polarizable by said two Zenerdiodes, and circuit means to prevent charging of the memory storage cellwhile power is supplied by the mains, said last named circuit meanscomprising other Zener diodes connected to be supplied by the powermains and a transistor polarizable by said other Zener diodes.
 9. Thatimprovement in load supplying systems according to claim 8 includingalso a centralizing system comprising a relay controlling transistor anda relay connected thereto, said last named transistor being renderedconductive by simultaneous presence of power in the mains and of adischarge current from the memory storage cell.
 10. That improvement inload supplying systems according to claim 7 wherein said means to effectdischarge of the memory storage cell at substantially constant valuecomprises a discharge circuit including a transistor and a resistorconnected for passage through it of discharge current from the memorystorage cell, said last-named transistor having an emitter which ispolarizable by the discharge current passing through the resistor. 11.That improvement in load supplying systems according to claim 1 whereinsaid storage battery recharging system for charging selectively at highand low charge rates includes means for effecting charging at theselected rates at respective different constant voltages, andtemperature sensitive means for controlling the time of high ratecharging of the storage battery as necessary.
 12. That improvement inload supplying systems wherein the load is alternatively supplied bypower mains and by a stand-by storage battery upon occurrence of failureat the power mains comprising a storage battery recharging systemincluding means to charge the battery selectively at fast high rate andmeans to charge the battery at slow low rate from the power mains, meansto control automatically the fast high rate charging time, saidlast-named means comprising a memory storage cell connected to becharged by the storage battery only while the latter is discharging intothe load on occurrence of power failure and proportionately to the totalamount of electricity actually discharged by the storage battery intothe load, and circuit means for delivering discharge current from theproportionately charged memory storage cell to activate the high ratecharging means of the storage battery upon restoration of power supplyin the mains, an additional low capacity storage cell connected to bemaintained in charged condition by power from the power mains andconnected to the high rate charging means to activate the latter upondischarge of such low capacity storage cell and serve as an additionalcontrol for establishing fast high rate charging of the storage battery,and manual control means connected for effecting such discharge of saidadditional low capacity storage cell.
 13. That improvement in loadsupplying system according to claim 1 wherein said means for chargingthe memory storage cell comprise transistors and wherein said meansresponsive to discharge of current of the charged memory storage cell onrestoration of power supply at the mains also includes transistors. 14.That improvement in load supplying systems according to claim 13 includetemperature compensation means for all said transistors.
 15. Thatimprovement in load supplying systems wherein the load alternatively issupplied by power from power mains, and by a stand-by storage batteryupon failure of power supply from the mains comprising a storage batteryrecharging system for charging the battery from the mains selectively ata high and low charge rates and comprising a memory storage cell of lowcapacity relative to that of the storage battery, circuit meansincluding transistors connected for effecting charging of the memorystorage cell by discharge current from the storage battery andproportionately to the total amount of current discharged therefromwhile the latter is supplying the load on failure of power from themAins, circuit means including transistors connected between the memorystorage cell and said battery recharging system to permit dischargecurrent flow from the proportionately charged memory storage cell onrestoration of power supply in the mains to activate said storagebattery charging system to high charge rate until discharge current flowfrom said proportionately charged memory storage cell substantiallyceases, and means to thereafter re-establish low charging rate of thestorage battery from said recharging system.
 16. That improvement inload supplying systems according to claim 15 including relay means tocut off supply of the load by the storage battery while power is beingsupplied by the mains.
 17. That improvement in load supplying systemsaccording to claim 15 including also circuit means comprisingtransistors and a relay connected to the battery recharging system todiscontinue automatically its charging at high rate and effectrestoration of charging at low rate at substantial cessation ofdischarge current flow from said memory storage cell.
 18. Thatimprovement in load supplying systems according to claim 15 includingmeans responsive to storage battery temperature and switching meansoperated thereby to change said battery recharging system from high rateto low rate charging irrespective of the charge condition of said memorystorage cell when the storage battery temperature exceeds a determinedvalue during high rate charging thereof.
 19. That improvement in loadsupplying systems wherein a load is alternatively supplied either bypower mains or a stand-by storage battery upon occurrence of powerfailure at the mains, comprising a storage battery recharging system forcharging the battery selectively at high and low charging rates, amemory storage device of low capacity relative to the stand-by storagebattery, means for charging said memory storage device to an extentdirectly proportionate to the total amount of current discharged by thestand-by battery while the latter is supplying current into the loadduring power failure, and automatic means responsive to operation of theproportionately charged memory storage device effective on restorationof power supply at the mains automatically to initiate and maintain highrate charging of the stand-by battery from said mains for a period oftime that is a function of the total charge received by the memorystorage device during actual discharge of the stand-by battery, andmeans for thereafter establishing low rate charging of said stand-bybattery from the mains.